1. Field of the Invention
Aspects of the present invention are directed to three-dimensional (3D) packaging thermal management and, more particularly, to a segmentation of a die stack for 3D packaging thermal management.
2. Description of the Background
Generally, an electronic package is a hardware component in which active devices, such as logic or memory devices, and passive devices, such as resistors and capacitors, are enclosed. The electronic package performs functions of an electronic system, such as those used inside a mobile phone, a personal computer, a digital music player, etc. Common electronic packages are classified as either flip-chip or wire-bond packages.
In a typical flip-chip electronic package, as shown in FIG. 1, a single die 10 is joined to a chip carrier 100 or substrate though electrical interconnects 130 called controlled collapse chip connections (C4) bumps. The chip carrier 100 is either a ceramic or organic material. The C4 may be encapsulated in an underfill material 160. A lid 120 (e.g., a cap or a hat) can be used to provide thermal cooling and/or mechanical protection. A thermal interface material (TIM) 150, which can be an elastomer, adhesive, gel or metal, may be disposed between the chip 10 and the lid 120. A bond 170, such as an elastomer, epoxy or mechanical fasteners, may be used to attach the lid 120 to the chip carrier 100. The chip carrier 100 may be further coupled to a secondary carrier 110 or a printed circuit board (PCB) via leads 140.
In order to increase bandwidth and function, one particular construction of an electronic package, which is shown in FIG. 2, involves horizontally attaching multiple dies 11, 12, 13 and 14 to a multi-chip-carrier 101. Here, the electronic package grows in dimension to accommodate the multiple dies 11, 12, 13 and 14 and presents cost and size-related reliability issues. In another construction of an electronic package, which is shown in FIG. 3, multiple dies 15 and 16-18 are vertically stacked onto a single-chip carrier 102.
Since a set of chips, resistors, capacitors and/or memory units may be provided in a particular die stack, it may be a complete functional unit requiring few external components. As such, use of the die stack in space-constrained environments, such as mobile phones and computers, may be valuable. Also, a stacked die can provide an increased electrical interconnect density with less latency and lower power consumption, which can greatly increase system performance. This is especially true with “multicore” chips where it is difficult to increase the bandwidth to memory adequately.
Despite its benefits, however, a problem with a die stack exists in that the upper die provides a thermal resistance along the primary heat flow path from the die stack and into the cooling lid (e.g., the lid 120 of FIG. 1). During normal operations, this thermal resistance causes an internal temperature of an electronic package with a die stack to increase as compared to that of a non-stacked electronic package. As a result, a performance of the electronic package with a die stack may be degraded.